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DG506A, DG507A, DG508A, DG509A
Data Sheet November 1999 File Number 3137.3
CMOS Analog Multiplexers
The DG506A, DG507A, DG508A and DG509A are CMOS Monolithic 16-Channel/Dual 8-Channel and 8-Channel/Dual 4-Channel Analog Multiplexers, which can also be used as demultiplexers. An enable input is provided. When the enable input is high, a channel is selected by the address inputs, and when low, all channels are off. A channel in the ON state conducts current equally well in both directions. In the OFF state each channel blocks voltages up to the supply rails. The address inputs and the enable input are TTL and CMOS compatible over the full specified operating temperature range. The DG506A, DG507A, DG508A and DG509A are pinout compatible with the industry standard devices.
Features
* Low Power Consumption * TTL and CMOS-Compatible Address and Enable Inputs * 44V Maximum Power Supply Rating * High Latch-Up Immunity * Break-Before-Make Switching * Alternate Source
Applications
* Data Acquisition Systems * Communication Systems * Signal Multiplexing/Demultiplexing * Audio Signal Multiplexing
Ordering Information
PART NUMBER DG506AAK DG506ACJ DG506ACY DG507ABK DG507ACJ DG507ACY TEMP. RANGE (oC) -55 to 125 0 to 70 0 to 70 -25 to 85 0 to 70 0 to 70 PACKAGE 28 Ld CERDIP 28 Ld PDIP 28 Ld SOIC 28 Ld CERDIP 28 Ld PDIP 28 Ld SOIC PKG. NO. F28.6 E28.6 M28.3 F28.6 E28.6 M28.3 PART NUMBER DG508AAK DG508ABK DG508ACJ DG509ACJ DG509ACY TEMP. RANGE (oC) -55 to 125 -25 to 85 0 to 70 0 to 70 0 to 70 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC PKG. NO. F16.3 F16.3 E16.3 E16.3 M16.3
Pinouts
DG506A (PDIP, CERDIP, SOIC) TOP VIEW
V+ 1 NC 2 NC 3 S16 4 S15 5 S14 6 S13 7 S12 8 S11 9 S10 10 S9 11 GND 12 NC 13 A3 14 28 D 27 V26 S8 25 S7 24 S6 23 S5 22 S4 21 S3 20 S2 19 S1 18 EN 17 A0 16 A1 15 A2
DG507A (PDIP, CERDIP, SOIC) TOP VIEW
V+ 1 DB 2 NC 3 S8B 4 S7B 5 S6B 6 S5B 7 S4B 8 S3B 9 S2B 10 S1B 11 GND 12 NC 13 NC 14 28 DA 27 V26 S8A 25 S7A 24 S6A 23 S5A 22 S4A 21 S3A 20 S2A 19 S1A 18 EN 17 A0 16 A1 15 A2
DG508A (PDIP, CERDIP) TOP VIEW
A0 1 16 A1 15 A2 14 GND 13 V+ 12 S5 11 S6 10 S7 9 S8
DG509A (PDIP, SOIC) TOP VIEW
A0 1 EN 2 V- 3 S1A 4 S2A 5 S3A 6 S4A 7 DA 8 16 A1 15 GND 14 V+ 13 S1B 12 S2B 11 S3B 10 S4B 9 DB
EN 2 V- 3 S1 S2 S3 S4 4 5 6 7
D8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
DG506A, DG507A, DG508A, DG509A Truth Tables
DG506A A3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ON SWITCH None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A1 X 0 0 1 1 A0 X 0 1 0 1 DG509A EN 0 1 1 1 1 ON SWITCH None 1A, 1B 2A, 2B 3A, 3B 4A, 4B A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 DG507A A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 ON SWITCH None 1 2 3 4 5 6 7 8
Logic "0" = VAL , VENL 0.8V, Logic "1" = VAH , VENH 2.4V.
Logic "0" = VAL , VENL 0.8V, Logic "1" = VAH , VENH 2.4V.
A0 , A1 , EN Logic "1" = VAH 2.4V, Logic "0" = VAL 0.8V. DG508A A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 ON SWITCH None 1 2 3 4 5 6 7 8
A0 , A1 , A2 , EN Logic "1" = VAH 2.4V, Logic "0" = VAL 0.8V
2
DG506A, DG507A, DG508A, DG509A Functional Diagrams
DG506A
S1 S2 S3 S4 S5 S6 S7 S8 D S9 S10 S11 S12 S13 S14 S15 S16 A0 A1 A2 A3 EN ADDRESS DECODER 1 OF 16 ENABLE 1 OF 4 S1B S2B S3B S4B S5B S6B S7B S8B A0 A1 A2 EN (ENABLE INPUT) DB ADDRESS DECODER 1 OF 8 ENABLE 1 OF 2 S1A S2A S3A S4A S5A S6A S7A S8A DA
DG507A
4 Line Binary Address Inputs (0 0 0 1) and EN = 5V Above example shows channel 2 turned ON. DG508A
S1 S2 S3 S4 S5 S6 S7 S8 A0 A1 A2 EN (ENABLE INPUT) D ADDRESS DECODER 1 OF 8
3 Line Binary Address Inputs (0 0 0) and EN = 5V Above example shows channels 1A and 1B turned ON. DG509A
S1A S2A S3A S4A S1B S2B S3B S4B DB DA
3 Line Binary Address Inputs (1 0 1) and EN = 1 Above example shows channel 6 turned ON.
2 Line Binary Address Inputs (0 0) and EN = 1 Above example shows channels 1A and 1B turned ON.
Schematic Diagram
V+ V+ SX
LOGIC TRIP POINT REF GND LOGIC AX INPUT OR EN VLOGIC INTERFACE AND LEVEL SHIFTER
DECODER +
-
AX
DX
TYPICAL SWITCH
3
DG506A, DG507A, DG508A, DG509A
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Digital Inputs, VS, VD (Note 1) . . . . . . . . . . . . . .(V- -2V) To (V+ +2V) Continuous Current, (Any Terminal Except S or D) . . . . . . . . . 30mA Continuous Current, (S or D) . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 40mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) 16 Ld CERDIP Package. . . . . . . . . . . . 75 20 28 Ld CERDIP Package. . . . . . . . . . . . 55 18 16 Ld PDIP Package . . . . . . . . . . . . . . 90 N/A 28 Ld PDIP Package . . . . . . . . . . . . . . 55 N/A 16 Ld SOIC Package . . . . . . . . . . . . . . 100 N/A 28 Ld SOIC Package . . . . . . . . . . . . . . 70 N/A Maximum Junction Temperature CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature "A" and "B" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 150oC "C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 125oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range "A" Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC "B" Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC "C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals on SX , DX, EN, or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified "A" SUFFIX "B" AND "C" SUFFIX
PARAMETER DYNAMIC CHARACTERISTICS Switching Time of Multiplexer, tTRANSITION Break-Before-Make Interval, tOPEN Enable Turn-ON Time, tON(EN) Enable Turn-OFF Time, tOFF(EN) OFF Isolation, OIRR Source OFF Capacitance, CS(OFF) DG506A, DG507A DG508A, DG509A Drain OFF Capacitance, CD(OFF) DG506A DG507A DG508A DG509A Charge Injection, Q DG506A, DG507A DG508A, DG509A DIGITAL INPUT CHARACTERISTICS Address Input Current, Input Voltage High, IAH Address Input Current Input Voltage Low, IAL VA = 2.4V VA = 15V
TEST CONDITIONS
(NOTE 4) (NOTE 3) (NOTE 4) (NOTE 4) (NOTE 3) (NOTE 4) MIN TYP MAX MIN TYP MAX UNITS s s s s dB
See Figure 1 See Figure 3 See Figure 2 See Figure 2 VEN = 0V, RL = 1k, CL = 15pF, VS = 7VRMS , f = 500kHz (Note 5) VS = 0V, VEN = 0V, f = 140kHz
-
0.6 0.2 1 0.4 68
1 1.5 1.0 -
-
0.6 0.2 1 0.4 68
-
VD = 0V, VEN = 0V, f = 140kHz See Figure 4 -
6 5
-
-
6 5
-
pF pF
45 23 25 12 6 4
-
-
45 23 25 12 6 4
-
pF pF pF pF pC pC A A A A
-10 VA = 0V -10 -10
-0.002 0.006 -0.002 -0.002
10 -
-10 -10 -10
-0.002 0.006 -0.002 -0.0002
10 -
VEN = 2.4V VEN = 0V
4
DG506A, DG507A, DG508A, DG509A
Electrical Specifications
TA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified (Continued) "A" SUFFIX PARAMETER TEST CONDITIONS "B" AND "C" SUFFIX
(NOTE 4) (NOTE 3) (NOTE 4) (NOTE 4) (NOTE 3) (NOTE 4) MIN TYP MAX MIN TYP MAX UNITS
ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) (Note 7) Sequence Each IS = -200A, VD = +10V Switch ON IS = -200A, VD = -10V VAL = 0.8V VAH = 2.4V -10V VS +10V r DS(ON)MAX - r DS ( ON )MIN r DS ( ON ) = ----------------------------------------------------------------------r DS ( ON )AVG VEN = 0V VEN = 0V VS = -10V, VD = +10V VS = +10V, VD = -10V DG507A VS = -10V, VD = +10V VS = +10V, VD = -10V DG508A VS = -10V, VD = +10V VS = +10V, VD = -10V DG509A VS = -10V, VD = +10V VS = +10V, VD = -10V Drain ON Leakage Current, (Note 6) Sequence Each ID(ON) Switch ON DG506A VD = VS(ALL) = +10V VAL = 0.8V VD = VS(ALL) = -10V VAH = 2.4V DG507A VD = VS(ALL) = +10V VD = VS(ALL) = -10V DG508A VD = VS(ALL) = +10V VD = VS(ALL) = -10V DG509A VD = VS(ALL) = +10V VD = VS(ALL) = -10V POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, IPositive Supply Current, I+ Standby Negative Supply Current, I- Standby VEN = 0V, VA = 0V (Standby) VEN = 5.0V, VA = 0V (Enabled) -1.5 -1.5 1.3 -0.7 1.3 -0.7 2.4 2.4 -1.5 -1.5 1.3 -0.7 1.3 -0.7 2.4 2.4 mA mA mA mA -10 -10 -5 -5 -10 -10 0.02 -0.03 0.007 -0.015 0.01 -0.015 0.005 -0.008 10 10 5 5 10 10 -20 -20 -10 -10 -20 -20 0.02 -0.03 0.007 -0.015 0.01 -0.015 0.005 -0.008 20 20 10 10 20 20 nA nA nA nA nA nA nA nA VS = +10V, VD = -10V VS = -10V, VD = +10V -1 -1 0.002 -0.005 1 1 -5 -5 0.002 -0.005 5 5 nA nA -15 270 230 +15 400 400 -15 270 230 +15 450 450 V
rDS(ON) Matching Between Channels
-
6
-
-
6
-
%
Source OFF Leakage Current, IS(OFF) Drain OFF Leakage Current, ID(OFF) DG506A
-10 -10 -5 -5 -10 -10
0.03 -0.06 0.015 -0.03 0.015 -0.03 0.007 -0.015
10 10 5 5 10 10 -
-20 -20 -10 -10 -20 -20
0.03 -0.06 0.015 -0.03 0.015 -0.03 0.007 -0.015
20 20 10 10 20 20 -
nA nA nA nA nA nA nA nA
5
DG506A, DG507A, DG508A, DG509A
Electrical Specifications
TA = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified "A" SUFFIX PARAMETER DIGITAL INPUT CHARACTERISTICS Address Input Current, Input VA = 2.4V Voltage High, IAH VA = 15V Address Input Current Input Voltage Low, IAL VEN = 2.4V VEN = 0V (Note 7) Sequence Each Switch ON VAL = 0.8V VAH = 2.4V VEN = 0V IS = -200A, VD = +10V IS = -200A, VD = -10V VA = 0V -30 -30 -30 30 A A A A V TEST CONDITIONS MIN (NOTE 3) TYP MAX "B" AND "C" SUFFIX MIN (NOTE 3) TYP MAX UNITS
ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) -15 +15 500 500 -
Source OFF Leakage Current, IS(OFF)
VS = +10V, VD = -10V VS = -10V, VD = +10V
-50
-
50 -
-
-
-
nA nA
Drain OFF Leakage Current, VEN = 0V ID(OFF) DG506A
VS = -10V, VD = +10V VS = +10V, VD = -10V VS = -10V, VD = +10V VS = +10V, VD = -10V VS = -10V, VD = +10V VS = +10V, VD = -10V VS = -10V, VD = +10V VS = +10V, VD = -10V
-300 -200 -200 -100
-
300 200 200 100 -
-
-
-
nA nA nA nA nA nA nA nA
DG507A
DG508A
DG509A
Drain ON Leakage Current, ID(ON) DG506A
(Note 6) Sequence Each Switch ON VAL = 0.8V VAH = 2.4V
VD = VS(ALL) = +10V VD = VS(ALL) = -10V VD = VS(ALL) = +10V VD = VS(ALL) = -10V VD = VS(ALL) = +10V VD = VS(ALL) = -10V VD = VS(ALL) = +10V VD = VS(ALL) = -10V
-300 -200 -200 -100
-
300 200 200 100 -
-
-
-
nA nA nA nA nA nA nA nA
DG507A
DG508A
DG509A
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, IPositive Standby Supply Current, I+ Negative Standby Supply Current, INOTES: 3. Typical values are for design aid only, not guaranteed and not subject to production testing. 4. The algebraic convention whereby the most negative value is a minimum, and the most positive value is a maximum, is used in this data sheet. 5. Off isolation = 20Log |VS |/|VD |, where VS = input to Off switch, and VD = output due to VS . 6. ID(ON) is leakage from driver into "ON" switch. 7. Parameter not tested. Parameter guaranteed by design or characterization. VEN = 0V, VA = 0V VEN = 5.0V, VA = 0V -3.2 -3.2 -3.2 -3.2 4.5 4.5 4.5 4.5 mA mA mA mA
6
DG506A, DG507A, DG508A, DG509A Test Circuits and Waveforms
+2.4V +15V V+ EN A3 A2 A1 LOGIC INPUT 50 -15V A0 GND S16 +10V SWITCH OUTPUT VO 1M 35pF DG506A (NOTE) S1 10V +2.4V +15V V+ EN DG507A S1B (NOTE) S1A THRU S8A , DA A2 S2B , AND S7B A1 LOGIC INPUT 50 -15V A0 GND S8B +10V SWITCH OUTPUT VO 1M 35pF 10V
S2 THRU S15
D V-
DB V-
NOTE: Similar connections for DG508A. FIGURE 1A. DG506A TEST CIRCUIT
NOTE: Similar connections for DG509A. FIGURE 1B. DG507A TEST CIRCUIT
3V LOGIC INPUT 50% 0 VS1 S1 ON 0.8VS1 SWITCH OUTPUT VO
tr < 20ns tf < 20ns
0
0.8VS8 VS8 S8 ON TRANSITION TIME TRANSITION TIME
FIGURE 1C. MEASUREMENT POINTS FIGURE 1. SWITCHING TIME
+15V V+ EN DG506A (NOTE) A3 A2 A1 A0 EN 50 GND V-15V D 1k SWITCH OUTPUT VO EN 35pF 50 S2 THRU S16 A0 A1 A2 GND DB V-15V 1k SWITCH OUTPUT VO 35pF S1 -5V EN DG507A (NOTE) S1A THRU S8A , DA , S2B THRU S8B V+ S1B -5V +15V
NOTE: Similar connections for DG508A. FIGURE 2A. DG506A TEST CIRCUIT
NOTE: Similar connections for DG509A. FIGURE 2B. DG507A TEST CIRCUIT
7
DG506A, DG507A, DG508A, DG509A Test Circuits and Waveforms
(Continued)
tr < 20ns tf < 20ns 50% tOFF (EN)
3V EN 0V tON (EN) 0V 50%
0.1VO SWITCH OUTPUT VO
VO
0.9VO
FIGURE 2C. MEASUREMENT POINTS FIGURE 2. ENABLE TIMES
+2.4V V+ EN ALL S AND DA DG506A DG507A (NOTE) +5V (VS) LOGIC INPUT 0V 3V tr < 20ns tf < 20ns +15V
A0 A1
VS A2 A3 GND 50 -15V DB V1k 35pF SWITCH OUTPUT VO SWITCH OUTPUT VO 0V tOPEN 50% 50%
LOGIC INPUT
NOTE: Similar connections for DG508A, DG509A. FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
+15V V+ EN DG506A (NOTE) A3 A2 A1 A0 LOGIC INPUT GND V1000pF -15V -15V D VO S1 A2 A1 A0 LOGIC INPUT GND DA OR DB V1000pF VO S1A, S1B EN DG507A (NOTE) V+ +15V
NOTE: Similar connections for DG508A. FIGURE 4A. DG506A TEST CIRCUIT
NOTE: Similar connections for DG509A. FIGURE 4B. DG507A TEST CIRCUIT
8
DG506A, DG507A, DG508A, DG509A Test Circuits and Waveforms
(Continued)
3V EN 0
VO
VO
VO is the measured voltage error due to charge injection. The charge transfer error in Coulombs is Q = CL x VO . FIGURE 4C. CHARGE INJECTION WAVEFORMS FIGURE 4. CHARGE INJECTION
Typical Performance Curves
550 V+ = +15V, V- = -15V 500 V+ = +10V, V- = -10V 450 V+ = +12V, V- = -12V V+ = +7.5V, V- = -7.5V 400 rDS(ON) () rDS(ON) () 350 300 250 200 150 100 50 0 -15 -10 -5 0 5 10 15 0 -55 -25 0 20 45 70 100 125 100 400 V+ = +15V V- = -15V VEN = 2.4V IO = -200A 300 +10V SIGNALS 200 +10V SIGNALS
ANALOG SIGNAL VOLTAGE (V)
TEMPERATURE (oC)
FIGURE 5. rDS(ON) vs ANALOG SIGNAL VOLTAGE vs SUPPLY VOLTAGE
FIGURE 6. TYPICAL rDS(ON) VARIATION WITH TEMPERATURE
9
DG506A Die Characteristics
DIE DIMENSIONS: 3810m x 2770m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kA 1.4kA Nitride: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG506A
NC NC V+ D V-
S16
S8
S15
S7
S14
S6
S13
S5
S12
S4
S11
S3
S10
S2
S9
S1
GND
NC
A3
A2
A1
A0
EN
10
DG507A Die Characteristics
DIE DIMENSIONS: 3810m x 2770m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kA 1.4kA Nitride: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG507A
NC DB V+ DA V-
S8B
S8A
S7B
S7A
S6B
S6A
S5B
S5A
S4B
S4A
S3B
S3A
S2B
S2A
S1B
S1A
GND
NC
NC
A2
A1
A0
EN
11
DG508A Die Characteristics
DIE DIMENSIONS: 3100m x 2083m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kA 1.4kAww Nitride: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG508A
EN A0 A1 A2
GND
VV+
S1
S5
S2
S6
S3 S4 D S8
S7
12
DG509A Die Characteristics
DIE DIMENSIONS: 3100m x 2083m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kA 1.4kA Nitride: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG509A
EN A0 A1 GND
V+
VS1B
S1A
S2B
S2A
S3B
S3A S4A DA DB
S4B
13
DG506A, DG507A, DG508A, DG509A Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
14
DG506A, DG507A, DG508A, DG509A Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
E28.6 (JEDEC MS-001-BF ISSUE D)
28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580 MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.600 BSC 0.115 28 0.700 0.200
2.54 BSC 15.24 BSC 2.93 28 17.78 5.08
15
DG506A, DG507A, DG508A, DG509A Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A MIN 0.0926 0.0040 0.013 0.0091 0.3977 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.4133 0.2992 MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 MAX 2.65 0.30 0.51 0.32 10.50 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
L
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 16 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 16 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
16
DG506A, DG507A, DG508A, DG509A Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992
B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
17
DG506A, DG507A, DG508A, DG509A Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
18
DG506A, DG507A, DG508A, DG509A Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.490 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 37.85 15.49 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 90o 28 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 90o 28 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
19

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